1. Field of the Invention
The present invention relates to a MOS-technology power device integrated structure, more particularly to a Vertical Double-Diffused power MOS (VDMOS) or an Insulated Gate Bipolar Transistor (IGBT), and to a manufacturing process thereof.
2. Discussion of the Related Art
MOS-technology power devices are particularly suitable for applications wherein high currents at high voltages must be switched in times of the order of some hundreds of nonoseconds. It is therefore necessary to have MOS-technology power devices capable of handling high powers in extremely short times.
Conventional MOS-technology power devices have a cellular structure including several thousand elementary cells integrated in a semiconductor substrate to form a bidimensional array; each elementary cell represents an elementary VDMOS and is connected in parallel to all the other cells, in order to contribute for a given fraction to the overall current of the power device.
MOS-technology power devices of this type are for example described in the U.S. Pat. Nos. 5,008,725, 4,593,302 and 4,680,853.
Each cell includes a polygonal P type body region (square or hexagonal) formed in a lightly doped N type layer; a polygonal source region is provided inside each body region; the polygonal source region defines a polygonal annular portion between the external edge of the source region and the edge of the body region; such polygonal annular portion, covered by a thin oxide layer (gate oxide) and a polysilicon layer (polysilicon gate), forms a channel region of the elementary VDMOS.
The polysilicon gate and the underlying gate oxide form a mesh over the surface of the lightly doped N type layer, since they substantially are continuous layers with openings over the center of the elementary cells. Elongated regions with no elementary cells are provided in the gate oxide and polysilicon layers; at this elongated regions the polysilicon layer is contacted by gate metal fingers extending from a gate metal pad. The remaining surface of the chip is covered by a source metal layer contacting the source regions of all the elementary cells.
The cellular structure allows achievement of high channel lengths per unit area; this in turn limits the voltage drop across the power device when it is in the "on" state (i.e. the so-called "on-state resistance" R.sub.D Son): this is an important parameter, because it is directly related to the steady-state power dissipation of the power device.
However, due to the fact that the resistivity of polysilicon is not negligible, a parasitic resistance is intrinsically introduced by the polysilicon layer in series between the gate metal pad and the gate of the cells; the farther a cell from a gate metal finger, the higher its gate resistance. Such a resistance, together with the input capacitances of the cells and with other parasitic capacitances (e.g. the parasitic capacitances between the polysilicon gate and the substrate in the area between the cells), forms an RC circuit which strongly affects the dynamic performances of the power device.
Although the polysilicon gate layer is normally doped to reduce its resistivity, the effects on the dynamic performances of the power device are limited.
A significant improvement would be obtained augmenting the number of gate metal fingers, thus reducing the spacing between them; this obviously reduces the gate resistance of the elementary cells, but at the expense of a reduction in the channel length per unit area, and thus with an increase in the R.sub.D Son.
Furthermore, since in order to maximize the chip area which contributes to the current conduction in the on state (active area) it is now common to provide a bonding pad for the source lead directly over the active area of the chip (a technique known as "bonding on active area"), the region of the chip where said bonding pad is formed cannot be traversed by gate metal finger, because otherwise a short-circuit would be caused between source and gate due to the bonding of the source lead. The area of the bonding pad is such that the regular distance between adjacent gate metal fingers cannot be respected. As a consequence, the portion of active area under the source bonding pad is the last to be affected by the gate signal, and the elementary VDMOS' in said portion of the active area are therefore the last to be turned on/off when the power device is driven on/off.
The parasitic capacitances can be controlled by using a thicker gate oxide: this however has an impact on the threshold voltage of the power device.
A reduction in the spacing between the cells also allows limitation of the parasitic capacitances, but again at the expense of an increase in the R.sub.D Son.
In view of the state of the art described, it is an object of the present invention to provide a new MOS-technology power device integrated structure which overcomes the above-mentioned problems; more specifically, the new MOS-technology power device structure shall have good dynamic performances but not at the expense of the steady-state performances.